FPGA LUT CIRCUIT SOFTWARE
The TTC, in conjunction with software and IC design engineers at the company's San Jose site, created the Altera FPGA Modeling Toolkit (FMT), which allows complete “virtual prototyping” of different FPGA architecture ideas. With the acquisition of Right Track CAD and the creation of the Toronto Technology Centre (TTC) in 2000, Altera brought together a senior team of FPGA architecture researchers from academia. Another major inefficiency is the replication of routing to the smaller LUTs when building a larger LUT and the creation of extra delays between LUTs which results in a non-optimized logic structure.ĭeveloping the Adaptive Logic Module (ALM) The problem with these architectures, however, is that logic elements built from smaller LUTs, as indicated in Fig 2, are inefficient and result in wasted resources when implementing smaller functions with less than k-inputs. Similarly a 5-LUT can be built from two 4-LUTs and a multiplexer, while a 6-LUT can be built with two 5-LUTs and a multiplexer. A 4-input Logic Element(LE) block diagram (Altera's Stratix FPGA family).Īlso, as illustrated in the lower half of Fig 2, larger LUTs can be formed from smaller LUTs and one or more multiplexers. A new core architecture that could efficiently pack more logic per logic element – thereby delivering higher performance at lower power and ultimately lowering the overall cost – had to be created.ġ. Hence, the traditional methodology of implementing logic in an FPGA on a 4-input LUT had to be fundamentally challenged through design innovation. In addition, with the dramatic increase in FPGA density, the critical path delays in the routing fabric dominated as the routing wires did not scale as well as transistors. Īs process geometries began shrinking to 90-nm and downward to 65-nm, the benefits of higher performance and increased density, although almost taken for granted, became available, but at the cost of higher power consumption in the core. For a long time, 4-input LUTs provided the best area-delay product and the Stratix (130-nm) core was based on the 4-input logic elements (LEs) shown in Fig 1. Also known as configuration memory (CRAM), these cells are stitched together using a set of multiplexers that select a bit to drive the output for any given function based on a 4-input mapping scheme. Until relatively recently, the majority of FPGA architectures were developed using 4-input lookup tables (LUTs), where each LUT is constructed from SRAM bits storing digital (0 or 1) information.
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